1. Field of the Invention
The invention generally relates to integrated semiconductor circuits, such as DRAM memory circuits, and methods for operating such circuits.
2. Background Information
FIG. 1 illustrates a section of a conventional DRAM memory that has circuits for transporting data from sense amplifiers SA to data outputs of the DRAM memory chip. The memory cell array is subdivided into individual cell blocks in the row or X direction, of which a first cell block 1 and a second cell block 2 are shown. A so-called sense amplifier or SA strip lies between two adjacent cell blocks, in which strip are arranged the primary sense amplifiers SA connected to the bit lines BL and CSL switches respectively connected to the individual sense amplifiers SA. Furthermore, the local data lines (LDQs), for example LDQ1.1, 1.2, 2.1, 2.2, 3.1 and 3.2, are routed in the SA strip 1. Additionally situated in the SA strips are MDQ/LDQ switches, which serve for connecting the LDQs to the MDQs in response to a control signal, and also charge equalization transistors LDQ-EQL, which serve for precharging the LDQ lines to a center level Vbleq and are fed with a corresponding potential Vbleq.
As can be seen in FIG. 1, the LDQs are subdivided into individual segments, for example into the LDQ segments 1, 2 and 3, in the column direction Y, and the CSL lines CSL1, CSL2, CSL3 and also the MDQ switches and the charge equalization transistors are present for each segment. The CSL lines pass via all of the blocks of the cell array. The same applies to the MDQs, which can be connected to the LDQs via the MDQ/LDQ switches. What cannot be seen in the schematic diagram of FIG. 1 is that, in reality, all of the LDQs and MDQs are constructed as complementary line pairs.
The MDQs are connected to secondary sense amplifiers SSA, arranged in the chip belt. Both the primary sense amplifiers SA and the secondary sense amplifiers SSA are embodied as differential amplifiers and process the differential signals fed to them on the complementary BLs or LDQs, on the one hand, and the MDQs, on the other hand. The MDQ/LDQ switches represent a 1 out of X selection of the LDQ segments to the same associated MDQ. Which LDQ is switched through to the MDQ by the associated MDQ/LDQ switch depends upon the selected word line (not shown in FIG. 1), and thus on the corresponding spread BL or the spread SAs.
To simplify the illustration, the complementary lines have been omitted from FIG. 1, and only individual lines are depicted in each case for MDQ and LDQ line pairs. Added to these are the above mentioned precharge control lines for LDQ and MDQ for the driving of the LDQ charge equalization transistors and of MDQ charge equalization transistors situated in the chip belt. The LDQ and MDQ, in the precharge case, are respectively connected to corresponding generators for Vbleq and Vblh. While the LDQ precharge takes place for all of the LDQs that are not connected to the MDQs, for the MDQ precharge it is necessary in each case for the active SSA block to be excluded from the precharge. This presupposes an LDQ-segment-specific control of the MDQ-EQL transistors.
A CSL, which represents the applied Y address, selects in each case two primary sense amplifiers SA in all of the SA strips via the driven CSL switches, even though only few SAs have actually evaluated data. In other words, the CSL signal passing through a plurality of cell blocks also drives non-active SAs, or SAs of blocks in which no word line is activated.
FIG. 2a shows, on the basis of a signal timing diagram, precharge potentials of an LDQ of a cell block which, from an initially active state, assumes the inactive state starting from the instant t1. The instant t1 represents the instant at which the LDQ is decoupled from the MDQ, brought about by the MDQ/LDQ switch signal going low. Two possible and different profiles of the LDQ precharge level are illustrated by dash-dotted lines.
A potential problem arises if the LDQ was unable to be precharged to Vbleq at the instant of the CSL pulse signal. If the LDQs were still at high bit line level, a voltage greater than the center level would be established on the non-spread bit line connected to the LDQ by means of the CSL pulse signal, which would be able to be lowered again to the center level only slowly.